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FX803 Audio Signalling Processor
SIGNAL INPUT BIAS DIGITAL NOISE (Rx) AUDIO IN INPUT AMPLIFIER VDD FILTER 1
Rx FILTER SWITCH
DIGITAL NOISE FILTER 2
QUALITY METER
PROGRAMABLE NOTONE TIMER
COMMAND DATA REPLY DATA C-BUS INTERFACE CHIP SELECT AND CONTROL LOGIC INTERRUPT SERIAL CLOCK LOGIC INPUT
GATE TIME GENERATOR
FREQUENCY COUNTER PROGRAMABLE (Tx PERIOD) TIMER
VBIAS
TONE 1 GENERATOR 5- / 2-TONE DTMF 1
LOW PASS FILTER
TONE 1 OUT
SUM IN SWITCHED SUM OUT V SS
SUMMING SWITCH CAL/CUES SWITCH
SUM OUT CAL/CUES OUT
VBIAS XTAL/CLOCK CLOCK GENERATOR XTAL AUDIO SWITCH IN
AUDIO SWITCH
CUES
SUMMING AMPLIFIER TONE 2 GENERATOR CUES / DTMF 2
CAL
LOW PASS FILTER
TONE 2 OUT
AUDIO SWITCH OUT
Fig.1 FX803 Audio Signalling Processor
FX803 Audio Signalling Processor
As part of the DBS 800 System, this audio signalling processor will provide an inband tone signalling facility for PMR radio systems. Signalling systems supported include Selcall (CCIR, ZVEI I, II and III, EEA), 2-Tone Selcall and Dual Tone Multi-Frequency (DTMF) encode. Using a non-predictive tone decoder and versatile encoders gives the FX803 the capability to work in any standard or non-standard tone system. This is a full-duplex device consisting of: q q q Two individual tone generators and a programmable (Tx) period timer. A tone decoder with programmable NOTONE Timer. An on-chip summing amplifier. Both tone generators can be individually placed into a power economical "Powersave" mode. A general purpose logic input, interfacing directly with the Status Register, is provided. This could be used as an auxiliary method of routeing digital information to the Controller via the "C-BUS." The output frequencies are produced from data loaded to the device, with a programmable, general purpose, on-chip timer available to indicate the tone transmit periods. A Dual Tone Multi-Frequency (DTMF) output is obtained by combining the 2 independent output frequencies in the integral summing amplifier. This Summing Amplifier output is also available for level adjustment. Tones produced by the FX803 can also be used in the DBS 800 system as modulation calibration inputs and for "CUE" audio indications for the operator. Received tones are measured and their frequency indicated to the Controller in the form of a received data word. A poor-quality or incoherent tone will, after a programmed period, indicate NOTONE. The FX803 is a low-power, 5-volt CMOS integrated circuit and is available in 24-pin DIL cerdip and 24-pin/lead plastic SMD packages.
For use with Single Tone or Selective Call systems. Under the control of the Controller, via "C-BUS," the FX803 will encode and transmit a single or pair of audio tones, in the frequency range 208Hz to 3kHz, simultaneously, and detect, decode and indicate the frequency of non-predicted input tones in the frequency range 313Hz to 6kHz.
Publication D/803/6 April 1998
Pin Number Function
J/LG/LS
1
DW
1 Xtal: The output of the on-chip clock oscillator. External components are required at this input when a Xtal input is used. See Figure 2.
2
2
Xtal/Clock: The input to the on-chip clock oscillator inverter. A Xtal or externally derived clock (fXTAL) should be connected here. See Figure 2.
3
3
Reply Data: The "C-BUS" serial data output to the Controller. The transmission of Reply Data bytes is synchronized to the Serial Clock under the control of the Chip Select input. This 3-state output is held at high-impedance when not sending data to the Controller. See Timing Diagrams.
4
5
Chip Select (CS): The "C-BUS" data loading control function. This input is provided by the Controller. Data transfer sequences are initiated, completed or aborted by the CS signal. See Timing Diagram.
5
6
Command Data: The "C-BUS" serial data input from the Controller. Data is loaded to this device in 8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the Serial Clock. See Timing Diagrams.
6
7
Logic Input: This `real-time' input is available as a general purpose logic input port which can be read from the Status Register. See Table 3.
7
8
Interrupt Request (IRQ): The output of this pin indicates an interrupt condition to the Controller, by going to a logic "0." This is a "wire-or able" output, allowing the connection of up to 8 peripherals to 1 interrupt port on the Controller. This pin has a low-impedance pulldown to logic "0" when active and a high-impedance when inactive. The System IRQ line requires one pullup resistor to VDD. The conditions that cause interrupts are indicated in the Status Register and are shown below: G/Purpose Timer Period Expired NOTONE Timer Period Expired Rx Tone Measurement Complete These interrupts are inactive during relevant Powersave conditions and can be disabled by Bits 5 and 6 in the Control Register.
8
4
No internal connection, connect to VSS.
9
9
No internal connection, connect to VSS.
10
10
Audio Switch In: The input to the stand-alone, on-chip Audio Switch. This switching function (Control Register Bit 7) may be used to break the system transmitter modulation path when it is required to provide a CUE (beep) from Tone Generator 2 to the loudspeaker via the FX806 PLMR Audio Processor.
11
11
Audio Switch Out: The output of the stand-alone, on-chip Audio Switch.
12
12
VSS: Negative Supply (Signal Ground).
2
Pin Number Function
J/LG/LS
13
DW
13 (Rx) Audio In: The received audio tone signalling input to the Input Amplifier. This input requires to be a.c. coupled and connected, using external components, to the Signal Input Bias pin. See Figure 2. Signal Input Bias: External components are required between this input and the (Rx) Audio In pin See Figure 2. VBIAS: The internal circuitry bias line, held at VDD/2 this pin must be decoupled to VSS by capacitor C2 See Figure 2. Tone 1 Out: Tone 1 Generator (2-/5- tone Selcall or DTMF 1) output. External gain and coupling components will be required at this output when operating in a complete DBS 800 audio installation. The frequency of this output is determined by writing to Tx Tone Generator 1 Register (Table 4). See Figure 2. Tone 2 Out: Tone 2 Generator (2-/5- tone Selcall, CUES or DTMF 2) output. External gain and coupling components will be required at this output when operating in a complete DBS 800 audio installation. The frequency of this output is determined by writing to Tx Tone Generator 2 Register (Table 5). See Figure 2. CAL/CUES Out: An auxiliary, selectable tone frequency output, providing a square wave CALibration signal from Tone 2 Generator or a sine wave CUES (beep) signal from the Summing Amplifier. The output mode (CAL or CUES) is selected by Bit 14 in the Tx Tone Generator 2 Register (Table 5). In a DBS 800 audio installation, this output should be connected to the Calibration Input of the FX806 PLMR Audio Processor. When Tone Generator 2 is set to VBIAS (NOTONE), the CAL output is pulled to VBIAS and during a powersave of Tone Generator 2 it is held at VSS. Sum In: The input to the on-chip Summing Amplifier. This amplifier is available for combining Tone 1 and Tone 2 outputs (DTMF). Gain and coupling components should be used at this input to provide the required system gains. See Figures 2 and 3. Sum Out: The output of the on-chip Summing Amplifier. Combined tones (1 and 2) are available at this output. See Figures 2 and 3. Switched Sum Out: The combined tone output available for transmitter modulation. The switch allows control of the FX803 final output to the FX806. Control of this switch is by Bit 4 of the Control Register. See Figures 2 and 3. No internal connection, connect to VSS. Serial Clock: The "C-BUS" serial clock input. This clock, produced by the Controller, is used for transfer timing of commands and data to and from the Audio Signalling Processor. See Timing Diagrams. VDD: Positive supply rail. A single +5-volt power supply is required. Levels and voltages within the Audio Signalling Processor are dependent upon this supply. NOTE: (i) Further information on external components and DBS 800 system integration of this microcircuit are contained in the System Support Document.
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22 23
22 23
24
24
"C-BUS" is CML's proprietary standard for the transmission of commands and data between a Controller and DBS 800 microcircuits. It may be used with any Controller, and can, if desired, take advantage of the hardware serial I/O functions embodied into many types of Controller. The "C-BUS" data rate is determined solely by the Controller.
3
External Components
VDD C6 XTAL SEE INSET BELOW R8 XTAL/CLOCK REPLY DATA CS
1 2 3 4
24 23 22 21 20
VDD SERIAL CLOCK VSS R6
*
SWITCHED SUM OUT SUM OUT SUM IN R3
*
COMMAND DATA
5
LOGIC INPUT IRQ
C5 TONE LEVEL and GAIN COMPONENTS
6 7 8 9
FX803J
19 18 17 16 15 14 13
CAL/CUES OUT TONE 2 OUT TONE 1 OUT
*
R4
*
AUDIO SWITCH IN AUDIO SWITCH OUT
*
10 11 12
VBIAS
R5 SIGNAL BIAS (Rx) AUDIO IN C1 C2 R2
R7
VSS
VSS INSET
XTAL
1
Component
R1 R2 *R3 *R4 *R5 *R6 *R7 R8 =
Value
1.0M 2.0M 100k 82.0k 122k 100k 100k 22.0k C1 C2 C3 C4 C5 C6 X1 = 0.1F 1.0F 33.0pF 33.0pF 22.0pF 1.0F 4.00MHz
X
R
1
1
FX803J
XTAL/CLOCK C4 C3 V
SS
2
fXTAL
Fig.2 Recommended External Components
Tolerance: R = 10% C = 20%
Notes
1. Xtal/clock circuitry components shown INSET are recommended in accordance with CML Application Note D/XT/1 April 1986. The DBS 800 System Support Document contains additional notes on the use of Xtal/ clock frequencies (fXTAL). It is recommended that, to improve screening and reduce noise levels around the FX803, Pins 8, 9 and 22 are connected to VSS. 3. Resistors marked with an asterisk (*) are System Components, calculated to operate in a system with other DBS 800 microcircuits. Figure 3 shows in detail, these components used in the System signal paths. R3, R4, R5, C5 - Tone mixing components to provide a 3dB tone-differential (twist) when used in a DTMF configuration. Single tone output levels are set independently or by the FX806 Modulator Drivers. R7 - Modulation level and matching for inputs to the FX806.
2.
AUDIO SWITCH IN 10 11
FROM FX806 "MAIN PROCESS OUT"
AUDIO SWITCH OUT
TO FX806 "SUM IN"
Part of FX803
CAL CUES TONE 2 OUT 17 BIAS
18
CAL/CUES OUT
TO FX806 "CALIBRATION IN"
21 SWITCHED SUM OUT
+
16 SUM IN 19
20
SUM OUT
-
TONE 1 OUT
SUMMING AMPLIFIER
Fig.3 Output Signal Switching
4
DBS 800 "TRANSMIT AUDIO" BUS
Controlling Protocol
Control of the FX803 Audio Signalling Processor's operation is by communication between the Controller and the FX803 internal registers on the "C-BUS," using Address/Commands (A/Cs) and appended instructions or data (see Figure 7). The use and content of these instructions is detailed in the following paragraphs and tables.
FX803 Internal Registers
FX803 internal registers are detailed below: Control Register (30H) - Write Only, control and configuration of the FX803. Status Register (31H) - Read Only, reporting of device functions. Rx Tone Frequency Register (32H) - Read Only, indicates frequency of the last received input. Rx NOTONE Timer Register (33H) - Write Only, setting of the Rx NOTONE period. Tx Tone Generator 1 Register (34H) - Write Only, setting the required output frequency from Tx Tone Generator 1. Tx Tone Generator 2 Register (35H) - Write Only, setting required output frequency from Tx Tone Generator 2. General Purpose Timer Register (36H) - Write Only, setting of a general purpose, sequential time period.
Address/Commands
The first byte of a loaded data sequence is always recognized by the "C-BUS" as an Address/Command (A/C) byte. Instruction and data transactions to and from this device consist of an Address/Command byte followed by either: (i) (ii) further instructions or data or, a Status or data Reply. Instructions and data are loaded and transferred, via "C-BUS," in accordance with the timing information given in Figures 7 and 8. Table 1 shows the list of A/C bytes relevant to the FX803. A complete list of DBS 800 "C-BUS" Address allocations is published in the System Support Document.
Command Assignment
General Reset Write to Control Register Read Status Register Read Rx Tone Frequency Write to NOTONE Timer Write to Tx Tone Gen. 1 Write to Tx Tone Gen. 2 Write to G/Purpose Timer
Address/Command (A/C) Byte Hex. Binary
MSB LSB
+
Data Byte/s
01 30 31 32 33 34 35 36
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1
0 0 0 1 1 0 0 1
1 0 1 0 1 0 1 0
+ + + + + + +
1 byte Instruction to Control Register 1 byte Reply from Status Register 2 byte Reply from Rx Tone Register 1 byte Instruction to NOTONE Register 2 byte Instruction to Tx Tone Gen. 1 2 byte Instruction to Tx Tone Gen. 2 1 byte Instruction to G/Purpose Timer
Table 1 "C-BUS" Address/Commands
0
1000
2000
3000
4000
5000
6000
Frequency (Hz) (Tx) TONE GENERATORS 1 and 2 1250Hz to 6000Hz (Rx) HIGH BAND (Rx) HIGH BAND (Rx) MID BAND 313Hz to 1500Hz Frequency (Hz)
0 1000 2000 3000 4000 5000 6000
208Hz to 3000Hz (Rx) EXTENDED BAND 625Hz to 3000Hz
Fig.4 FX803 Frequencies
5
Controlling Protocol ......
"Write to Control Register"
- A/C 30H, followed by 1 byte of Command Data.
Setting
Audio Switch See the Signal Switching diagram (Figure 3) and DBS 800 Document for application examples. General Purpose Timer Should be set up before interrupts are enabled, as a General Reset command will set the timer period to 00H - 0ms (permanent interrupt). Interrupt Enable Instructions Status Bits 0, 1 and 2 are produced regardless of the state of these settings. Band Selection Bits 2 and 3 set the required frequency range (see Figure 4, FX803 Frequencies). Summing Switch To break the FX803 drive to the FX806 PLMR Audio Processor (see Figure 3, Signal Switching). Interrupt Designation Decoder Interrupts: No Tone Timer and Rx Tone Measurement. Transmitter Interrupt: G/Purpose Timer Interrupt.
Control Bits
Transmitted First Audio Switch Enable Disable
G/Purpose Timer Interrupt Enable Disable Decoder Interrupts Enable Disable Summing Switch Enable Disable
MSB Bit 7 1 0 6 1 0 5 1 0 4 1 0 3 0
0 1 1
2 0
1 0 1
Band Selection High Band Mid Band Extended Band Do Not use this setting Set to "0" Set to "0"
1 0 0 0
Table 2 Control Register
"Read Status Register"
Reading
MSB Bit 7 0 6 0 5 0 4 0 3 1 0 2 1
- A/C 31H, followed by 1 byte of Reply Data.
Status Bits
Received First Set to "0"
Set to "0" Set to "0" Set to "0" Logic Input Status "1" "0" G/Purpose Timer Period Expired (IRQ generated if enabled) (Table 2) NOTONE Timer Period Expired (IRQ generated if enabled) (Table 2) Rx Tone Measurement Complete (Interrupt Generated) Interrupt Requests (IRQ) Interrupts on this device are available to draw the attention of the Controller to a change in the condition of the bit in the Status Register. However Bits are set in the Status Register irrespective of the setting of interrupt enable bits (Table 2) and these changes may be recognized by `polling' the register. General Purpose Timer Period Set to a logic "1" when the timer period has expired. Cleared to a logic "0," i By a read of the Status Register or, ii New G/Purpose Timer information or, iii General Reset Command NOTONE Timer Period Set to a logic "1" when the timer period has expired. Cleared to a logic "0," i By a read of the Status Register or, ii New NOTONE Timer information or, iii General Reset Command Rx Tone Measurement Set to a logic "1" when the Rx Tone measurement is complete. Cleared to a logic "0," i By a read of the Status Register or, ii General Reset Command
1 1
0 1
Table 3 Status Register
6
Controlling Protocol ......
Tx Tone Generator Registers 1 and 2
Each Tx Tone Generator is controlled individually by writing a two-byte command to the relevant Tx Tone Generator Register. The format of this command word, which is different for each tone generator, is shown below with the calculations required for tone frequency (fTONE) generation described in the following text.
"Write to Tx Tone Generator 1 Register" - A/C 34H followed by 2 bytes of Command Data.
MSB (loaded first) 15 14 Bit Numbers 13 12 11 10 9 8 7 6 5 4 3 2 LSB (loaded last) 1 0
"0"
"0"
Enable
VBIAS/
These 13 bits (0 to 12) are used to produce a binary number, designated "A." "A" is used in the formulas below to set the Tx Tone 1 frequency (fTONE 1). Bit 13 at logic "1" = Tone 1 Output at VBIAS (NOTONE). "0" = Tone 1 Output Enabled. Bits 14 and 15 (MSB) must be logic "0."
The binary number produced by bits 0 to 12 (MSB) is designated "A." If "A" = all logic "0" then Tx Tone Generator 1 is Powersaved.
Table 4 Setting Tx Tone Generator 1
"Write to Tx Tone Generator 2 Register" - A/C 35H followed by 2 bytes of Command Data.
MSB (loaded first) 15 14 "0" Bit Numbers 13 12 11 10 9 8 7 6 5 4 3 2 LSB (loaded last) 1 0
CAL/ CUES
VBIAS/ Enable
These 13 bits (0 to 12) are used to produce a binary number, designated "B." "B" is used in the formulas below to set the Tx Tone 2 frequency (fTONE 2). Bit 13 at logic "1" = Tone 1 Output at VBIAS (NOTONE). "0" = Tone 1 Output Enabled. Bit 14 at logic "1" = Squarewave CAL Output. "0" = Sinewave CUES Output. Bit 15 (MSB) must be a logic "0."
The binary number produced by bits 0 to 12 (MSB) is designated "B." If "B" = all logic "0" then Tx Tone Generator 2 is Powersaved.
Table 5 Setting Tx Tone Generator 2
Notes (1) Programming Tone Generator 2 to VBIAS (NOTONE) (Bit 13) will place the CAL/CUES Output at VBIAS via a 40k internal resistor. (2) Programming Tone Generator 2 to Powersave will place the CAL/CUES Output at VSS. (3) If both Tone Generators (1 and 2) are Powersaved, the Summing Amplifier is also Powersaved.
Calculations
As can be seen from Tables 4 and 5 (above), a binary number ("A" or "B" - Bits 0 to 12) is loaded to the respective Tx Tone Generator. The formulas shown below are used to calculate the required output frequency. Required Tx Tone output frequency XTAL/clock frequency Input Data Word (Bits 0 to 12) = = = fTONE1 or 2 fXTAL "A" or "B"
Formula
fTONE (HZ) =
fXTAL (HZ) 4 x "A" (or "B")
or
Input "A" (or "B") = fXTAL (HZ) 4 x fTONE (HZ)
Tx Tone Frequencies
With reference to Tables 4 and 5 (above), whilst Input Data Words "A" or "B" can be programmed for frequencies outside the stated limits of 208Hz and 3000Hz, any output frequencies obtained may not be within specified parameters (see "Specification" page).
7
Controlling Protocol ......
"Read Rx Tone Frequency Register"
- A/C 32H, followed by 2 bytes of Reply Data.
Measurement of Rx Signal Frequency (SINPUT)
The measurement details given on Pages 10 and 11 are for a Xtal/clock frequency (fXTAL) of 4.032MHz, a scaling formula for other values of fXTAL is given at the bottom of this page. The input audio signal (SINPUT) is filtered and measured in the Frequency Counter over a specified "measurement period" (9.125 ms or 18.250 ms). The measuring function counts the number of complete input cycles occurring within the measurement period and then the number of measuring-clock cycles necessary to make up the period. When the count period of a successful decode is complete, the Rx Tone Measurement bit in the Status Register, and the Interrupt bit (if enabled) are set. The Rx Tone Frequency Register will now indicate the signal frequency (SINPUT) in the form of 2 bytes (1 and 0) as illustrated in Figure 6 below.
Measurement Period
Complete Input Cycle Complete Input Cycle Complete Input Cycle Complete Input Cycle Complete Measuring Clock Input Cycles Cycle
FILTERED AUDIO INPUT SIGNAL 2 x S INPUT
N
Fig.5 Measurement of a Mid or High Band Rx Frequency
R
The Integer (N) - Byte 1
A binary number representing `twice the number of complete input audio cycle periods' counted during the specified measurement period, which is: High Band Decode Mid Band Decode Extended Band Decode = = = 9.125 ms 18.250 ms 9.125 ms = = = "t" "t" "t"
The Remainder (R) - Byte 0
A binary number representing the remainder part, R, of 2 x Input Signal Frequency (SINPUT). `R = number of specified measuring-clock cycles' required to complete the specified measurement period (See N). The clock-cycle frequencies are: High Band Decode = 56.00 kHz Mid Band Decode = 28.00 kHz Extended Band Decode = 56.00 kHz
See the bottom of this page for "t" and "f" scaling factors
= = =
"f" "f" "f"
(REPLY DATA) (MSB) - TRANSMITTED FIRST
Byte 1 12 11 10 9 8 7 6 5
Byte 0 4 3
(REPLY DATA) (LSB) - TRANSMITTED LAST
15
14
13
2
1
0
"0" "0"
Integer (N)
"0" "0"
Remainder (R)
Fig.6 Format of the Rx Tone Frequency Register
fXTAL Scaling Factors
The calculations above are for an fXTAL of 4.032MHz. The following formulas enable the calculation of these values using any Xtal value. Note: fXTAL values are stated in MHz. "t"scaled "f"scaled = "t" x 4.032 fXTAL fXTAL 4.032
=
"f" x
8
Controlling Protocol ......
Frequency Measurement Formulae
To assist in the production of `look-up' tables and limit-values in the Controller and provide guidance upon the determination of N and R from a measured frequency, the following formulae show the derivation of the Rx frequency, S INPUT, from the measured data bytes (N and R), Figure 6.
High Band Measurement
SINPUT - High Band In the measurement period of 9.125ms, there are Nh cycles at 2SINPUT and Rh clock cycles at 56.000kHz. so Nh + 2 x SINPUT From which SINPUT = Rh 56000 = 9.125ms
Nh and Rh - High Band
The measurement period = 9.125ms Clock Frequency = 56.000kHz The measured frequency = 2 x SINPUT c/s In the measurement period there are: 2 x SINPUT x 9.125 x 10-3 cycles [1] Nh is the lower integer value of this decimal number: Nh = INT (9.125 x 10-3 x 2 x SINPUT) Rh = (9.125 x 10-3 - Nh ) x 56000 2 x SINPUT [4] [5]
28000 x Nh (511 - Rh)
Hz
Rh is rounded to the nearest integer of this decimal number:
Mid Band Measurements
SINPUT - Mid Band
In the measurement period of 18.250ms, there are Nm cycles at 2SINPUT and Rm clock cycles at 28.000kHz. so Nm + 2 x SINPUT From which SINPUT = Rm 28000 = 18.250ms
Nm and Rm - Mid Band
The measurement period = 18.250ms Clock Frequency = 28.000kHz The measured frequency = 2 x SINPUT c/s In the measurement period there are: 2 x SINPUT x 18.250 x 10-3 cycles Nm is the lower integer value of this decimal number: 14000 x Nm Hz (511 - Rm) [2] Nm Rm = = INT (18.250 x 10-3 x 2 x SINPUT) (18.250 x 10-3 - Nm ) x 28000 2 x SINPUT [6] [7] Rm is rounded to the nearest integer of this decimal number:
Extended Band Measurements
SINPUT - Extended Band
In the measurement period of 9.125ms, there are Ne cycles at SINPUT and Re clock cycles at 56.000kHz. so Ne SINPUT + Re 56000 = = 9.125ms
Ne and Re - Extended Band
The measurement period = Clock Frequency = The measured frequency = In the measurement period there are: SINPUT x 9.125 x 10-3 cycles [3] Ne Re = = 9.125ms 56.000kHz SINPUT c/s
Ne is the lower integer value of this decimal number: From which SINPUT 56000 x Ne (511 - Re) Hz INT (9.125 x 10-3 x SINPUT) (9.125 x 10-3 - Ne ) x 56000 SINPUT [8] [9] Re is rounded to the nearest integer of this decimal number:
9
Controlling Protocol ......
"Write to the Rx NOTONE Timer Register" - A/C 33H followed by 1 byte of Command Data.
Setting
MSB 76 0 0 3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Function/Period
Operation of the Rx NOTONE Timer
4 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
5 0 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Transmitted Bit 7 First These 4 bits must be "0"
High/Extended Band period (ms) 0 " 20 1% 40 " 60 " 80 " 100 " 120 " 140 " 160 " 180 " 200 " 220 " 240 " 260 " 280 " 300 " Mid Band 0 40 1% 80 " 120 " 160 " 200 " 240 " 280 " 320 " 360 " 400 " 440 " 480 " 520 " 560 " 600 "
2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
An Rx NOTONE period is that period when no signal or a consistently bad-quality signal is received. The Rx NOTONE Timer can be employed to indicate to the Controller that a NOTONE situation has existed for a predetermined period. This timer register can be written-to and set in any mode of the FX803. The NOTONE Timer period is `primed' by writing to the NOTONE Timer Register (33H) using the settings given in Table 6. "Priming" sets the timing period; this period can only start directly after a frequency (tone) measurement has been successfully completed. The NOTONE Timer is a one-shot timer being reset only by successful tone measurements. If the quality of the received signal drops to an unusable level the NOTONE Timer will start its run-down. On completion of the preset period, the NOTONe Timer Period Expired bit in the Status Register and the Interrupt (when enabled, Table 2) are set. Upon detection of the Interrupt, the Status Register should be read by the Controller to ascertain the source of the Interrupt. The NOTONe Timer Period Expired bit is cleared: i By a read of the Status Register or, ii New NOTONE Timer information or, iii General Reset command This timer is set to 00H (0ms) by a General Reset command.
Table 6 Rx NOTONE Timer Settings
The following situations may be encountered by the NOTONE Timer circuitry:
No Signal
The NOTONE Timer can only start its run down on completion of a valid frequency measurement.
Signal Fades after a Valid Tone Measurement
The timer will start to run down when the signal becomes unreadable to the device. At the end of the "primed" period the NOTONe Timer Period Expired bit in the Status Register and the Interrupt will be set.
No Signal after a Valid Tone Measurement
The timer will start to run down when the last Rx Tone Measurement complete bit is set. At the end of the "primed" period the NOTONe Timer Period Expired bit in the Status Register and the Interrupt will be set.
Signal Appears after the Timer has Started
If the frequency measurement is more than 75% complete when the timer period expires, neither the NOTONE bit nor the Interrupt will be set unless that frequency measurement is subsequently aborted.
10
Controlling Protocol ......
"Write to General Purpose Timer Register" - A/C 36H followed by 1 byte of Command Data.
Setting MSB 7 6 0 0 3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Function/Period
Operation of the General Purpose Timer
5 0 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
4 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Transmitted Bit 7 First These 4 bits must be "0"
High/Extended Mid Band Band Reset Timer and Start Timing Period of 0 0 " 10 ms 1% 20 ms 1% 20 " 40 " 30 " 60 " 40 " 80 " 50 " 100 " 60 " 120 " 70 " 140 " 80 " 160 " 90 " 180 " 100 " 200 " 110 " 220 " 120 " 240 " 130 " 260 " 140 " 280 " 150 " 300 "
2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
This timer, which is not dedicated to any specific function within the FX803, can be employed within the DBS 800 system to indicate time-elapsed periods of between 10ms and 150ms in the High/Extended Band, 20ms and 300ms in the Mid Band, to the Controller. Setting of the timer is by loading a single-byte data word via the "C-BUS," as indicated in Table 7 (left), to the FX803 via the Command Data line. The timer will be reset and the run-down started on completion of Timer Data Word loading. When the programmed time period has expired, the General Purpose Timer Expired bit (Bit 2) in the Status Register and the Interrupt (if enabled) are set. The General Purpose Timer Expired bit is cleared: i By a read of the Status Register, or ii New G/P Timer information, or iii General Reset command. When the programmed time period has expired, this timer will reset, restart and continue sequencing until; i New G/P Timer information is written, or ii A General Reset command. The General Purpose Timer Expired bit and the Interrupt will remain set until cleared. This timer is set to 00H (0ms) by a General Reset command.
Table 7 General Purpose Timer Settings
Powersave
Various sections of the FX803 can be placed independently into a power economical condition. Table 8 (below) gives a brief summary of the inactive, power-economical states available to the FX803.
Powersaved Section
Tone Encoder 1 Tone Encoder 2 Summing Amplifier
Instruction Source
Tx Tone Gen.1 Reg. (34H) Tx Tone Gen.2 Reg. (35H) All bits = "0" All bits = "0"
Table
4 5
This action is automatic when both Tone Encoders are in the powersave condition.
Table 8 FX803 Powersave Functions
Powersave Conditions
Xtal/Clock and "C-BUS": This circuitry is always active, on all DBS 800 microcircuits, under any powered/powersaved conditions.
11
Controlling Protocol ......
Interrupt Requests
An Interrupt (IRQ), when enabled, is provided by the FX803 to indicate the following conditions to the Controller.
NOTONE Timer Period Expired
Enabled: By Control Register Bit 5. Set: When the preset Notone Flag is set. Identified: By Status Register Bit 1. Cleared: By reading the Status Register.
G/Purpose Timer Period Expired
Enabled: By Control Register Bit 6. Set: When the General Purpose Timer has timed out. Identified: By Status Register Bit 2. Cleared: By reading the Status Register.
Rx Tone Measurement Complete
Enabled: By Control Register Bit 5. Set: When an Rx Frequency Measurement has been successfully completed. Identified: By Status Register Bit 0. Cleared: By reading the Status Register.
On recognition of the "Read Status" Command byte, the interrupt output is cleared, the Status Bits are transferred to the Controller via the "C-BUS" Reply Data line and the internal Status Bits are cleared.
Operational Recommendations
It is recommended that, following initial System power-up a General Reset command is sent to the FX803. Receive Sequence 1. 2. 3. 4. 5. Send Control Command for Rx: Select Midband/Highband and Digital Filter length. Disable transmitters, if desired by writing to Tone Frequency registers. Prime the NOTONE Timer by sending the required period byte. Enable Decoder interrupts as desired. When a valid tone has been detected by a successfully completed measurement the Status Register is set to "Tone Measurement Complete" and an interrupt sent to the C. The C examines the Status Register, if tone measurement is complete, reads in the Rx Tone Frequency in the form N + R (Figure 6). Rx Tone Measurement Complete interrupts are periodically sent to the C unless NOTONE is detected, in which case a NOTONE Interrupt is sent. 4. 5. Transmit Control Sequence 1. Set Tone Frequency Generators to VBIAS (setting both tone generators (Bit 13 = "1")) during the transmitter initialization period. Send Control Command for Tx: Select Sum/Switched Sum o/p and Audio Switch states. Send General Purpose (GP) Timer information for the VBIAS (NOTONE) transmitter initialization period (Step 1). This will initiate the timer. Enable the General Purpose Timer interrupt. C waits for "GP Timer Expired;" Reads the Status Register to check interrupt due to timer; Resets the Status Bit. If required, the C sends the next timer period followed by the next tone(s) frequency information. A new timer period sent will reset the timer, otherwise the timer is self-sequencing. The C monitors the interrupts and repeats 5 & 6 as required. After last loaded tone the C turns off the Tone Generator(s) by setting tone outputs to VBIAS (NOTONE) (Tables 4 and 5).
2.
3.
6.
6. 7.
7.
General Reset
Upon Power-Up the "bits" in the FX803 registers will be random (either "0" or "1"). A General Reset Command (01H) will be required to "reset" all microcircuits on the "C-BUS," and has the following effect upon the FX803. Control Reg. Status Reg. Bits 0, 1, 2.) NOTONE Timer Reg. Tone Gen. 1 Reg. (2 bytes) Tone Gen. 2 Reg. (2 bytes) Gen/Purpose Reg. Set as 00H Set as 00H Set as 00H Set as 0000H Set as 0000H Set as 00H
Glossary of Abbreviations
Below is a list of abbreviations used within this Data Sheet. fXTAL SINPUT fTONE Xtal/clock frequency Audio input signal Tone frequency
Sets the FX803 to: Encoder High Band (625Hz to 3000Hz) - with interrupts disabled, both timers set to 00H. It is recommended that both timers are set-up before interrupts are enabled, to prevent initial, undesired interrupts.
12
Timing Information
Timing Diagrams
Figure 7 shows the timing parameters for two-way communication between the Controller and the FX803 on the "C-BUS." Figure 8 shows, in detail, the timing relationships for "C-BUS" information transfer.
CHIP SELECT
t CSOFF
t CSE
SERIAL CLOCK
t NXT t CK
t NXT
t CSH
COMMAND DATA
7
MSB
6
5
4
3
2
1
0
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
REPLY DATA
ADDRESS/COMMAND BYTE 7
MSB
FIRST DATA BYTE
LAST DATA BYTE
t HIZ
6 5 4 3 2 1 0
LSB
7
6
5
4
3
2
1
0
Logic level is not important
FIRST REPLY DATA BYTE
LAST REPLY DATA BYTE
Fig.7 "C-BUS" Timing Information
NOT TO SCALE
Parameter
tCSE tCSH tCSOFF tNXT tCK tCH tCL tCDS tCDH tRDS tRDH tHIZ
Min.
2.0 4.0 2.0 4.0 2.0 500 500 250 0 250 50.0 -
Typ.
- - - - - - - - - - - -
Max.
- - - - - - - - - - - 2.0
Unit
s s s s s ns ns ns ns ns ns s
Notes (1) Command Data is transmitted to the peripheral MSB (Bit 7) first, LSB (Bit 0) last. Reply Data is read from the FX803 MSB (Bit 7) first, LSB (Bit 0) last. (2) Data is clocked into the FX803 and into the Controller on the rising Serial Clock edge. (3) Loaded data instructions are acted upon at the end of each individual, loaded byte. (4) To allow for differing Controller serial interface formats, the FX803 will work with either polarity Serial Clock pulses.
t CK t CL t CH t CDH tCDS
COMMAND DATA (from C) 70% VDD 30% VDD SERIAL CLOCK (from C)
tRDH tRDS
REPLY DATA (to C)
Fig.8 "C-BUS" Timing Relationships
13
NOT TO SCALE
Specification
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply voltage Input voltage at any pin (ref VSS = 0V) Sink/source current (supply pins) (other pins) Total device dissipation @ TAMB 25C Derating Operating temperature range: FX803J FX803DW/LG/LS Storage temperature range: FX803J FX803DW/LG/LS -0.3 to 7.0V -0.3 to (VDD + 0.3V) +/- 30mA +/- 20mA 800mW Max. 10mW/C -40C to +85C (cerdip) -40C to +85C (plastic) -55C to +125C (cerdip) -40C to +85C (plastic)
Operating Limits
All device characteristics are measured under the following conditions unless otherwise specified: VDD = 5.0V. TAMB = 25C. Xtal/Clock (fXTAL) = 4.032MHz. Audio Level 0dB ref: = 308mVrms @ 1kHz (60% deviation, FM). Noise Bandwidth = 5.0kHz Band-Limited Gaussian.
Characteristics
Static Values Supply Voltage Supply Current (Decoder + Both Timers) (Decoder + Both Timers + One Tx only) (All Functions Enabled) Analogue Impedances (Rx) Audio Input Summing Amp Input Switch Tones 1 and 2 Outputs CAL/CUES Output Summing Outputs
See Note
Min.
Typ.
Max.
Unit
4.5 - - - - - - - - -
5.0 2.0 4.0 5.0 20.0 20.0 1.0 10.0 5.0 10.0
5.5 - - - - - - - - -
V mA mA mA M M k k k k
Dynamic Values Digital Interface Input Logic "1" Input Logic "0" Output Logic "1" (IOH = -120A) Output Logic "0" (IOL = 360A) IOUT Tristate (Logic "1" or "0") Input Capacitance IOX (VOUT = 5.0V)
1 1 2 3 3 1 4
3.5 - 4.6 - - - -
- - - - - - -
- 1.5 - 0.4 4.0 7.5 4.0
V V V V A pF A
Overall Performance Rx - Decoding High-Band Sensitivity Tone Response Time Good Signal Tone-to-Noise Ratio = 0dB Frequency Band Measurement Resolution Measurement Accuracy
- 5 5, 6 - - 625 - -
-20.0 - -
- 30.0 40.0 3000 - -
dB ms ms Hz % %
9
0.2 0.5
14
Specification ......
Characteristics See Note Min. Typ. Max. Unit
Rx - Decoding ...... Mid-Band Sensitivity Tone Response Time Good Signal Tone-to-Noise Ratio = 0dB Frequency Band Measurement Resolution Measurement Accuracy Extended-Band Sensitivity Tone Response Time Good Signal Frequency Band Measurement Resolution Measurement Accuracy
- 7 6, 7 - - 313 - -
-20.0 - -
- 60.0 80.0 1500 - -
dB ms ms Hz % %
9
0.2 0.5
- 5 - 1250 - -
-20.0 -
- 20.0 6000 - -
dB ms Hz % %
9
0.2 0.5
Tx - Encoders 1 and 2 Tone Frequency Period (1/fTONE) Error Tone Amplitude Total Harmonic Distortion Rise Time to 90% Fall Time to 10% Frequency Change Time
8
208 - -1.0 - - - -
- - - 3/fTONE - 3/fTONE
3000 1.0 1.0 5.0 - 5.0 -
Hz s dB % secs ms secs
Timers General Purpose Timing Period Range High-Band Mid-Band Rx NOTONE Timing Period Range High-Band Mid-Band Xtal/Clock Frequency (f XTAL)
10.0 20.0
150 300
ms ms
20.0 40.0 3.9 -
300 600 6.0
ms ms MHz
Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Device control pins; Serial Clock, Command Data, and CS. Reply Data output. Reply Data and IRQ outputs. Leakage current into the "Off" IRQ output. Measurement Period = 9.125ms. Decode Probability = 0.993. Measurement Period = 18.250ms. When set to Powersave. For a good input signal. The use of the FX803 at Xtal/clock frequencies above 4.0MHz will cause a shift in the overall performance parameters.
15
Package Outlines
The FX803 is available in the package styles outlined below. Mechanical package diagrams and specifications are detailed in Section 10 of this document. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top.
Handling Precautions
The FX803 is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage.
FX803DW 24-pin plastic S.O.I.C.
(D2)
FX803J
24-pin cerdip DIL
(J4)
NOT TO SCALE
NOT TO SCALE
Max. Body Length Max. Body Width
15.57mm 7.59mm
Max. Body Length Max. Body Width
32.00mm 13.36mm
FX803LG 24-pin quad plastic encapsulated bent and cropped (L1)
FX803LS
24-lead plastic leaded chip carrier (L2)
NOT TO SCALE
NOT TO SCALE
Max. Body Length Max. Body Width
10.25mm 10.25mm
Max. Body Length Max. Body Width
10.40mm 10.40mm
Ordering Information
FX803DW FX803J 24 pin plastic S.O.I.C. 24-pin cerdip DIL (D2) (J4) FX803LG 24-pin encapsulated bent and cropped (L1) FX803LS 24-lead plastic leaded chip carrier (L2)
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry.
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached.
Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com
D/CML (D)/1 February 2002

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